
Data Sheet ADP5586
Rev. 0 | Page 3 of 44
SPECIFICATIONS
VDD = 1.8 V to 3.3 V, T
A
= T
J
= −40°C to +85°C, unless otherwise noted.
1
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY VOLTAGE
VDD Input Voltage Range VDD 1.65 3.6 V
Undervoltage Lockout Threshold UVLO
VDD
UVLO active, VDD falling 1.2 1.3 V
UVLO inactive, VDD rising 1.4 1.6 V
SUPPLY CURRENT
Standby Current I
STNBY
VDD = 1.65 V 1 4 μA
VDD = 3.3 V 1 10 µA
Operating Current (One Key Press) I
SCAN1
Scan = 10 ms, CORE_FREQ = 50 kHz,
scan active, 300 kΩ pull-up, VDD = 1.65 V
30 40 µA
SCAN2
Scan = 10 ms, CORE_FREQ = 50 kHz,
scan active, 300 kΩ pull-up, VDD = 3.3 V
PULL-UP, PULL-DOWN RESISTANCE
Pull-Up
Option 1 50 100 150 kΩ
Option 2 150 300 450 kΩ
Pull-Down 150 300 450 kΩ
INPUT LOGIC LEVEL (
RST
, SCL, SDA, R0, R1,
R2, R3, R4, R5, C0, C1, C2, C3, C4)
Input Voltage
Logic Low V
IL
0.3 × VDD V
IH
Input Leakage Current (Per Pin) V
I-LEAK
0.1 1 µA
PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1,
R2, R3, R4, R5, C0, C1, C2, C3, C4
Output Voltage
Logic Low V
OL1
Sink current = 10 mA, maximum of five
GPIOs active simultaneously
0.4 V
V
OL2
Sink current = 10 mA, all GPIOs active
simultaneously
0.5 V
Logic High V
OH
Source current = 5 mA 0.7 × VDD V
Logic High Output Leakage Current
(Per Pin)
V
OH-LEAK
0.1 1 µA
OPEN-DRAIN OUTPUT LOGIC LEVEL (
INT
, SDA)
Output Voltage
Logic Low
INT
V
OL3
I
SINK
= 10 mA 0.4 V
SDA V
OL4
I
SINK
= 20 mA 0.4 V
Logic High Output Leakage Current
(Per Pin)
OH-LEAK
Logic Propagation Delay 125 300 ns
Flip-Flop (FF) Hold Time
2
0 ns
FF Setup Time
2
175 ns
GPIO Debounce
2
70 µs
Internal Oscillator Frequency
3
OSC
FREQ
720 800 880 kHz
1
All limits at temperature extremes are guaranteed via correlation, using standard statistical quality control (SQC). Typical values are at T
A
= 25°C, VDD = 1.8 V.
2
Guaranteed by design.
3
All timers are referenced from the base oscillator and have the same ±10% accuracy.
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