Universal Remote Control R7 - SPECS SHEET Manual de usuario Pagina 19
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Data Sheet ADP5589
Rev. B | Page 19 of 52
REGISTER INTERFACE
Register access of the ADP5589 is acquired via its I
2
C-compatible
serial interface. The interface can support clock frequencies of
up to 1 MHz. If the user is accessing the FIFO or key event
counter (KEC), FIFO/KEC updates are paused. If the clock
frequency is very low, events may not be recorded in a timely
manner. FIFO or KEC updates can happen up to 23 μs after an
interrupt is asserted because of the number of I
2
C cycles required
to perform an I
2
C read or write. This delay should not present
an issue to the user.
Figure 27 shows a typical write sequence for programming an
internal register. The cycle begins with a start condition, followed
by the hard coded 7-bit device address, which for the ADP5589
is 0x34, followed by the R/
W
bit set to 0 for a write cycle. The
ADP5589 acknowledges the address byte by pulling the data line
low. The address of the register to which data is to be written is
sent next. The ADP5589 acknowledges the register pointer byte
by pulling the data line low. The data byte to be written is sent
next. The ADP5589 acknowledges the data byte by pulling the
data line low. A stop condition completes the sequence.
Figure 28 shows a typical multibyte write sequence for program-
ming internal registers. The cycle begins with a start condition
followed by the 7-bit device address (0x34), followed by the
R/
W
bit set to 0 for a write cycle. The ADP5589 acknowledges
the address byte by pulling the data line low. The address of the
register to which data is to be written is sent next. The ADP5589
acknowledges the register pointer byte by pulling the data line
low. The data byte to be written is sent next. The ADP5589
acknowledges the data byte by pulling the data line low. The
pointer address is then incremented to write the next data byte,
until it finishes writing the n data byte. The ADP5589 pulls the
data line low after every byte, and a stop condition completes
the sequence.
Figure 29 shows a typical byte read sequence for reading internal
registers. The cycle begins with a start condition followed by the
7-bit device address (0x34), followed by the R/
W
bit set to 0 for
a write cycle. The ADP5589 acknowledges the address byte by
pulling the data line low. The address of the register from which
data is to be read is sent next. The ADP5589 acknowledges the
register pointer byte by pulling the data line low. A start condi-
tion is repeated, followed by the 7-bit device address (0x34),
followed by the R/
W
bit set to 1 for a read cycle. The ADP5589
acknowledges the address byte by pulling the data line low. The
8-bit data is then read. The host pulls the data line high (no
acknowledge), and a stop condition completes the sequence.
START
0 = WRIT
E
7-BIT DEVICE ADDRESS
ADP5589 ACK
8-BIT REGISTER POINTER 8-BIT WRITE DATA00 0 0
ADP5589 ACK
ADP5589 ACK
STOP
09714-026
Figure 27. I
2
C Single-Byte Write Sequence
START
0 = WRIT
E
7-BIT DEVICE ADDRESS
ADP5589 ACK
8-BIT REGISTER POINTER WRITE BYTE 1 WRITE BYTE 2 WRITE BYTE n00 0 0 0 0 0
ADP5589 ACK ADP5589 ACK ADP5589 ACK ADP5589 ACK
ADP5589 ACK
STOP
09714-028
Figure 28. I
2
C Multibyte Write Sequence
START
0 = WRITE
7-BIT DEVICE ADDRESS 7-BIT DEVICE ADDRESS
ADP5589 ACK
8-BIT REGISTER POINTER 8-BIT READ DATA00 0 10 1
REPEAT START 1 = READ
ADP5589 ACK ADP5589 ACK
NO ACK
STOP
09714-027
Figure 29. I
2
C Single-Byte Read Sequence
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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