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ADP5589 Data Sheet
Rev. B | Page 8 of 52
DEVICE ENABLE
When sufficient voltage is applied to VDD and the
RST
pin is
driven with a logic high level, the ADP5589 starts up in standby
mode with all settings at default. The user can configure the
device via the I
2
C interface. When the
RST
pin is low, the
ADP5589 enters a reset state and all settings return to default.
The
RST
pin features a debounce filter.
DEVICE OVERVIEW
The ADP5589 contains 19 multiconfigurable input/output pins.
Each pin can be programmed to enable the device to carry out
its various functions, as follows:
• Keypad matrix decoding (11-column by 8-row matrix
maximum).
• General-purpose I/O expansion (up to 19 inputs/outputs).
• PWM generation.
• Clock division of externally supplied source.
• Dual logic function building blocks (up to three inputs,
one output).
• Two reset generators.
All 19 input/output pins have an I/O structure, as shown in
Figure 6.
I/O
VDD
100kΩ
I/O
DRIVE
DEBOUNCE
300kΩ
300kΩ
09714-005
Figure 6. I/O Structure
Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or
pulled down with a 300 kΩ resistor. For logic output drive, each
I/O has a 5 mA PMOS source and a 10 mA NMOS sink for
push-pull type output. For open-drain output situations, the
5 mA PMOS source is not enabled. For logic input applications,
each I/O can be sampled directly or, alternatively, sampled
through a debounce filter.
The I/O structure shown in Figure 6 allows for all GPI and GPO
functions, as well as PWM and clock divide functions. For key
matrix scan and decode, the scanning circuit uses the 100 kΩ or
300 kΩ resistor for pulling up keypad row pins and the 10 mA
NMOS sinks for grounding keypad column pins (see the Key
Scan Control section for details about key decoding).
Configuration of the device is carried out by programming an
array of internal registers via the I
2
C interface. Feedback of
device status and pending interrupts can be flagged to an
external processor via the
INT
pin.
The ADP5589 is offered with three feature sets. Table 5 lists the
options that are available for each model of the ADP5589.
Table 5. Available Options
Models Description
ADP5589ACPZ-00-R7
ADP5589ACBZ-00-R7
All GPIOs pulled up (default option)
ADP5589ACPZ-01-R7
ADP5589ACBZ-01-R7
Reset pass-through
1
ADP5589ACPZ-02-R7
ADP5589ACBZ-02-R7
Pull-down on special function pins
2
1
Reset pass-through implies that the RESET1 output (R4) follows the logic
level of the reset input pin,
RST
, after the oscillator has been enabled.
2
Special function pins are defined as R0 (Row 0), R3 (Row 3), R4 (Row 4), C4
(Column 4), C6 (Column 6), and C9 (Column 9).
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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