Universal Remote Control R7 - SPECS SHEET Manual de usuario Pagina 15
- Pagina / 40
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Data Sheet ADP5585
Rev. C | Page 15 of 40
REGISTER INTERFACE
Register access to the ADP5585 is acquired via its I
2
C-compatible
serial interface. The interface can support clock frequencies of
up to 1 MHz. If the user is accessing the FIFO or key event
counter (KEC), FIFO/KEC updates are paused. If the clock
frequency is very low, events may not be recorded in a timely
manner. FIFO or KEC updates can happen up to 23 μs after an
interrupt is asserted because of the number of I
2
C cycles required
to perform an I
2
C read or write. This delay should not present
an issue to the user.
Figure 23 shows a typical write sequence for programming an
internal register. The cycle begins with a start condition, followed
by the hard coded 7-bit device address, which for the ADP5585
is 0x34, followed by the R/
W
bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The address of the register to which data is to be written
is sent next. The ADP5585 acknowledges the register pointer
byte by pulling the data line low. The data byte to be written is
sent next. The ADP5585 acknowledges the data byte by pulling
the data line low. A stop condition completes the sequence.
Figure 24 shows a typical multibyte write sequence for program-
ming internal registers. The cycle begins with a start condition
followed by the 7-bit device address (0x34 for all models except
the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/
W
bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The address of the register to which data is to be written
is sent next. The ADP5585 acknowledges the register pointer
byte by pulling the data line low. The data byte to be written is
sent next. The ADP5585 acknowledges the data byte by pulling
the data line low. The pointer address is then incremented to
write the next data byte, until it finishes writing the n data byte.
The ADP5585 pulls the data line low after every byte, and a stop
condition completes the sequence.
Figure 25 shows a typical byte read sequence for reading inter-
nal registers. The cycle begins with a start condition followed
by the 7-bit device address (0x34 for all models except the
ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/
W
bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data line
low. The address of the register from which data is to be read is
sent next. The ADP5585 acknowledges the register pointer byte
by pulling the data line low. A start condition is repeated,
followed by the 7-bit device address (0x34 for all models except
the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/
W
bit set to 1 for a read cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The 8-bit data is then read. The host pulls the data line
high (no acknowledge), and a stop condition completes the
sequence.
START
0 = WRITE
7-BIT DEVICE ADDRESS
ADP5585 ACK
8-BIT REGISTER POINTER 8-BIT WRITE DATA0000
ADP5585 ACK
ADP5585 ACK
STOP
09841-022
Figure 23. I
2
C Single Byte Write Sequence
START
0 = WRITE
7-BIT DEVICE ADDRESS
ADP5585 ACK
8-BIT REGISTER POINTER WRITE BYTE 1 WRITE BYTE 2 WRITE BYTE n00 0 0 0 0 0
ADP5585 ACK ADP5585 ACK ADP5585 ACK ADP5585 ACK
ADP5585 ACK
STOP
09841-023
Figure 24. I
2
C Multibyte Write Sequence
START
0 = WRITE
7-BIT DEVICE ADDRESS 7-BIT DEVICE ADDRESS
ADP5585 ACK
8-BIT REGISTER POINTER 8-BIT READ DATA00 0 1 0 1
REPE
A
T ST
A
RT 1 = READ
ADP5585 ACK ADP5585 ACK
NO ACK
STOP
09841-024
Figure 25. I
2
C Single Byte Read Sequence
- ADP5585 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- THEORY OF OPERATION 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- ADP5585 Data Sheet 10
- 09841-012 11
- 09841-013 11
- Data Sheet ADP5585 13
- 09841-020 14
- Interrupts 14
- REGISTER INTERFACE 15
- Rev. C 16
- REGISTER MAP 17
- ID Register 0x00 19
- INT_STATUS Register 0x01 19
- Status Register 0x02 19
- FIFO_1 Register 0x03 19
- FIFO_2 Register 0x04 20
- FIFO_3 Register 0x05 20
- FIFO_4 Register 0x06 20
- Rev. C 21
- Rev. C 22
- GPI_STATUS_A Register 0x15 23
- GPI_STATUS_B Register 0x16 23
- RPULL_CONFIG_A Register 0x17 24
- RPULL_CONFIG_B Register 0x18 24
- RPULL_CONFIG_C Register 0x19 25
- RPULL_CONFIG_D Register 0x1A 25
- GPI_EVENT_EN_A Register 0x1D 26
- GPI_EVENT_EN_B Register 0x1E 26
- DEBOUNCE_DIS_A Register 0x21 28
- DEBOUNCE_DIS_B Register 0x22 28
- GPO_DATA_OUT_A Register 0x23 28
- GPO_DATA_OUT_B Register 0x24 29
- GPO_OUT_MODE_A Register 0x25 29
- GPO_OUT_MODE_B Register 0x26 29
- RESET1_EVENT_A Register 0x29 30
- RESET1_EVENT_B Register 0x2A 31
- RESET1_EVENT_C Register 0x2B 31
- RESET2_EVENT_A Register 0x2C 31
- RESET_CFG Register 0x2E 31
- PWM_OFFT_LOW Register 0x2F 32
- PWM_OFFT_HIGH Register 0x30 32
- PWM_ONT_LOW Register 0x31 32
- PWM_ONT_HIGH Register 0x32 32
- PWM_CFG Register 0x33 32
- LOGIC_CFG Register 0x34 33
- LOGIC_FF_CFG Register 0x35 33
- POLL_TIME_CFG Register 0x37 34
- PIN_CONFIG_A Register 0x38 34
- PIN_CONFIG_B Register 0x39 34
- PIN_CONFIG_C Register 0x3A 34
- GENERAL_CFG Register 0x3B 35
- INT_EN Register 0x3C 35
- APPLICATIONS DIAGRAM 36
- OUTLINE DIMENSIONS 37
Relacionado con productos y manuales para Controles remotos Universal Remote Control R7 - SPECS SHEET
(30 paginas)
(72 paginas)
(35 paginas)
(319 paginas)© 2020, manymanuals.es. Todos los derechos reservados | 0.035 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales