
ADP5585 Data Sheet
Rev. C | Page 32 of 40
Bit(s) Bit Name Access Description
Defines the length of time that the reset events must be active before a reset
signal is generated. All events must be active at the same time for the same
duration. RESET_TRIG_TIME[2:0] is common to both RESET1 and RESET2.
000 = immediate.
001 = 1.0 sec.
010 = 1.5 sec.
011 = 2.0 sec.
100 = 2.5 sec.
101 = 3.0 sec.
110 = 3.5 sec.
1 to 0 RESET_PULSE_WIDTH[1:0] Read/write
Defines the pulse width of the reset signals. RESET_PULSE_WIDTH[1:0] is common
to both RESET1 and RESET2.
00 = 500 µs.
01 = 1 ms.
10 = 2 ms.
11 = 10 ms.
PWM_OFFT_LOW Register 0x2F
Table 55. Register 0x2F, PWM_OFFT_LOW Bit Descriptions
Bit(s) Bit Name Access Description
7 to 0 PWM_OFFT_LOW_BYTE[7:0] Read/write Lower eight bits of PWM off time.
PWM_OFFT_HIGH Register 0x30
Table 56. PWM_OFFT_HIGH Bit Descriptions
Bit(s) Bit Name Access Description
Upper eight bits of PWM off time.
PWM_ONT_LOW Register 0x31
Table 57. PWM_ONT_LOW Bit Descriptions
Bit(s) Bit Name Access Description
Lower eight bits of PWM on time.
PWM_ONT_HIGH Register 0x32
Table 58. PWM_ONT_HIGH Bit Descriptions
Bit(s) Bit Name Access Description
7 to 0 PWM_ONT_HIGH_BYTE[7:0] Read/write Upper eight bits of PWM on time. Note that updated PWM times are not latched
until this byte is written to. PWM count times are referenced from the internal
oscillator. The fastest oscillator setting is 500 kHz (2 µs increments). Therefore, the
maximum period is
2 µs × 2
16
= 131 ms
This gives PWM frequencies from 500 kHz down to 7.6 Hz.
PWM_CFG Register 0x33
Table 59. PWM_CFG Bit Descriptions
7 to 3 N/A Reserved.
1 = PWM signal AND’ed with an externally supplied PWM signal (C3).
1 PWM_MODE Read/write Defines PWM mode.
0 = continuous.
1 = executes one PWM period, then sets PWM_EN to 0.
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